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1 3377b?flash?9/03 features complies with intel ? low-pin count (lpc) interface specification revision 1.1 ? supports both firmware hub (fwh) and lpc memory read and write cycles auto-detection of fwh and lpc memory cycles ? can be used as fwh for intel 8xx, e7xxx, and e8xxx series chipsets ? can be used as lpc flash for non-intel chipsets flexible, optimized sectoring for bios applications ? 16-kbyte top boot sector, two 8-kbyte sectors, one 32-kbyte sector, three 64-kbyte sectors ? or memory array can be divided into four uniform 64-kbyte sectors for erasing two configurable interfaces ? fwh/lpc interface for in-system operation ? address/address multiplexed (a/a mux) interface for programming during manufacturing fwh/lpc interface ? operates with the 33 mhz pci bus clock ? 5-signal communication interface supporting byte reads and writes ? two hardware write protect pins: tbl for top boot sector and wp for all other sectors ? five general-purpose input (gpi) pins for system design flexibility ? identification (id) pins for multiple device selection ? sector locking registers for individual sector read and write protection a/a mux interface ? 11-pin multiplexed address and 8-pin data interface ? facilitates fast in-system or out-of-system programming single voltage operation ? 3.0v to 3.6v supply voltage for read and write operations industry-standard package options ? 32-lead plcc ? 40-lead tsop description the at49lh002 is a flash memory device designed for use in pc and notebook bios applications. the device complies with version 1.1 of intel?s lpc interface specifica- tion, providing support for both fwh and lpc memory read and write cycles. the device can also automatically detect the memory cycle type to allow the at49lh002 to be used as a fwh with intel chipsets or as an lpc flash with non-intel chipsets. 2-megabit firmware hub and low-pin count flash memory at49lh002 pin configurations plcc note: [ ] designates a/a mux interface. 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 [a7] gpi1 [a6] gpi0 [a5] wp [a4] tbl [a3] id3 [a2] id2 [a1] id1 [a0] id0 [i/o0] fwh0/lad0 ic [ic] gnd nc nc vcc init [oe] fwh4/lframe [we] res [rdy/bsy] res [i/o7] 4 3 2 1 32 31 30 14 15 16 17 18 19 20 [i/o1] fwh1/lad1 [i/o2] fwh2/lad2 gnd [i/o3] fwh3/lad3 [i/o4] res [i/o5] res [i/o6] res gpi2 [a8] gpi3 [a9] rst [rst] nc vcc clk [r/c] gpi4 [a10] tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 nc [ic] ic nc nc nc nc [a10] gpi4 nc [r/c] clk vcc nc [rst] rst nc nc [a9] gpi3 [a8] gpi2 [a7] gpi1 [a6] gpi0 [a5] wp [a4] tbl gnd vcc fwh4/lframe [we] init [oe] res [rdy/bsy] res [i/o7] res [i/o6] res [i/o5] res [i/o4] vcc gnd gnd fwh3/lad3 [i/o3] fwh2/lad2 [i/o2] fwh1/lad1 [i/o1] fwh0/lad0 [i/o0] id0 [a0] id1 [a1] id2 [a2] id3 [a3]
2 at49lh002 3377b?flash?9/03 the sectoring of the at49lh002?s memory array has been optimized to meet the needs of today?s bios applications. by optimizing the size of the sectors, the bios code memory space can be used more efficiently. because certain bios code modules must reside in their own sectors by themselves, the wasted and unused memory space that occurred with previous generation bios flash memory devices can be greatly reduced. this increased memory space efficiency allows additional bios routines to be developed and added while still main- taining the same overall device density. the memory array of the at49lh002 can be sectored in two ways simply by using two differ- ent erase commands. using one erase command allows the device to contain a total of seven sectors comprised of a 16-kbyte boot sector, two 8-kbyte sectors, a 32-kbyte sector, and three 64-kbyte sectors. the 16-kbyte boot sector is located at the top (uppermost) of the device?s memory address space and can be hard ware write protected by using the tbl pin. alternatively, by using a different erase command, the memory array can be arranged into four even erase sectors of 64-kbyte each, allowing the top 64-kbyte region to be used as the boot sector. the tbl pin, when used with the second erase command, will hardware write protect the entire top 64-kbyte region against erasure. the at49lh002 supports two hardware interfaces: the fwh/lpc interface for in-system operations and the a/a mux interface for programming during manufacturing. the interface configuration (ic) pin of the device provi des the control between these two interfaces. an internal command user interface (cui) serves as the control center between the device inter- faces and the internal operation of the nonvolatile memory. a valid command sequence written to the cui initiates device automation. specifically designed for use in 3-volt systems, the at49lh002 supports read, program, and erase operations with a supply voltage range of 3.0v to 3.6v. no separate voltage is required for programming and erasing. the at49lh002 utilizes fixed program and erase times, independent of the number of pro- gram and erase cycles that have occurred. therefore, the system does not need to be calibrated or correlated to the cumulative number of program and erase cycles. block diagram flash memory array y-gating control logic clk fwh4/lframe fwh/lad[3:0] r/c a[10:0] i/o[7:0] oe we rdy/bsy id[3:0] gpi[4:0] ic rst fwh/lpc interface a/a mux interface y-decoder address latch x-decoder i/o buffers and latches tbl wp interface control and logic init
3 at49lh002 3377b?flash?9/03 pin description table 1 provides a description of each of the device pins. most of the pins have dual functionality in that they are used for both the fwh/lpc interface as well as the a/a mux interface. device memory map sector type size (bytes) address range 6 sub-sector 16k 03c000h - 03ffffh 5 sub-sector 8k 03a000h - 03bfffh 4 sub-sector 8k 038000h - 039fffh 3 sub-sector 32k 030000h - 037fffh 2 main sector 64k 020000h - 02ffffh 1 main sector 64k 010000h - 01ffffh 0 main sector 64k 000000h - 00ffffh table 1. signal descriptions symbol name and function interface type fwh/lpc a/a mux ic interface communication : the ic pin determines which interface is operational. if the ic pin is held high, then the a/a mux interface is enabled, and if the ic pin is held low, then the fwh/lpc interface is enabled. the ic pin must be set at power-up or before returning from a reset condition and cannot be changed during device operation. the ic pin is internally pulled-down with a resistor valued between 20 k ? and 100 k ? , so connection of this pin is not necessary if the fwh/lpc interface will always be used in the system. if the ic pin is driven high to enable the a/a mux interface, then the pin will exhibit some leakage current. x x input clk fwh/lpc clock : this pin is used to provide a clock to the device. this pin is usually connected to the 33 mhz pci clock and adheres to the pci specification. this pin is used as the r/c pin in the a/a mux interface. x input fwh4/ lframe fwh input/lpc frame : this pin is used to indicate the start of a fwh or lpc data transfer operation. the pin is also used to abort a fwh or lpc cycle in progress. this pin is used as the we pin in the a/a mux interface. x input fwh/ lad[3:0] fwh/lpc address and data : these pins are used for fwh/lpc bus information such as addresses, data, and command inputs/outputs. these pins are used as the i/o[3:0] pins in the a/a mux interface. x input/ output rst interface reset : the rst pin is used for both fwh/lpc and a/a mux interfaces. when the rst pin is driven low, write operations are inhibited, internal automation is reset, and the fwh/lad[3:0] pins (when using the fwh/lpc interface) are put into a high-impedance state. when the device exits the reset state, it will default to the read array mode. x x input
4 at49lh002 3377b?flash?9/03 init processor reset/initialize : the init pin is used as a second reset pin for in-system operation and functions identically to the rst pin. the init pin is designed to be connected to the chipset?s init signal. the maximum voltage to be applied to the init pin depends on the processor?s or chipset?s specifications. systems must take care to not violate processor or chipset specifications regarding the init pin voltage. this pin is used as the oe pin in the a/a mux interface. x input tbl top boot sector lock : when the tbl pin is held low, program and erase operations cannot be performed to the 16-kbyte top boot sector regardless of the state of the sector locking registers. in addition, the tbl pin will either protect the 16-kbyte top boot sector or the uppermost 64-kbyte region against erasures depending on which sector erase command has been issued to the device. please refer to the sector protection section for more details. if the tbl pin is held high, then hardware write protection for the top boot sector will be disabled. however, register-based sector protection will still apply. the state of the tbl pin does not affect the state of the sector locking registers. this pin is used as the a4 pin in the a/a mux interface. x input wp write protect : the wp pin is used to protect all remaining sectors that are not being used for the top boot region. see the ?sector protection? section on page 16 for more details. if the wp pin is high, then hardware write protection for all of the sectors except the top boot sector will be disabled. register-based sector protection, however, will still apply. the state of the wp pin does not affect the state of the sector locking registers. this pin is used as the a5 pin in the a/a mux interface. x input id[3:0] identification inputs : these four pins are part of the mechanism that allows multiple devices to be attached to the same bus. the strapping of these pins is used to assign an id to each device. the boot device must have id[3:0] = 0000, and it is recommended that all subsequent devices should use sequential up-count strapping (e.g., 0001, 0010, 0011, etc.). values presented on the id[3:0] pins are only recognized when the device is operated as a fwh device. if the device is operating as an lpc flash, then the id[3:0] pins are ignored. the id[3:0] pins are internally pulled-down with resistors valued between 20 k ? and 100 k ? when using the fwh/lpc interface, so connection of these pins is not necessary if only a single device will be used in a system. any pins intended to be low may be left floating. any id pin driven high will exhibit some leakage current. these pins are used as the a[3:0] pins in the a/a mux interface. fwh input gpi[4:0] general-purpose inputs : the individual gpi pins can be used for additional board flexibility. the state of the gpi pins can be read, using the fwh/lpc interface, through the gpi register. the gpi pins should be at their desired state before the start of the pci clock cycle during which the read is attempted, and they should remain at the same level until the end of the read cycle. the voltages applied to the gpi pins must comply with the devices v ih and v il requirements. any unused gpi pins must not be left floating. these pins are used as the a[10:6] pins in the a/a mux interface. x input a[10:0] address inputs : these pins are used for inputting the multiplexed address values when using the a/a mux interface. the addresses are latched by the rising and falling edge of r/c pin. x input table 1. signal descriptions (continued) symbol name and function interface type fwh/lpc a/a mux
5 at49lh002 3377b?flash?9/03 i/o[7:0] data inputs/outputs : the i/o pins are used in the a/a mux interface to input data and commands during write cycles and to output data during memory array, status register, and identifier code read cycles. data is internally latched during a write cycle. the i/o pins will be in a high-impedance state when the outputs are disabled. x input/ output r/c row/column address select : in the a/a mux interface, the r/c pin is used to latch the address values presented on the a[10:0] pins. the row addresses (a10 - 0) are latched on the falling edge of r/c , and the column addresses (a17 - a11) are latched on the rising edge of r/c . x input oe output enable : the oe pin is used in the a/a mux interface to control the device?s output buffers during a read cycle. the i/o[7:0] pins will be in high-impedance state when the oe pin is deasserted (high). x input we write enable : the we pin is used in the a/a mux interface to control write operations to the device. x input rdy/bsy ready/busy : the rdy/bsy pin provides the device?s ready/busy status when using the a/a mux interface. the rdy/bsy pin is a reflection of status register bit 7, which is used to indicate whether a program or erase operation has been completed. use of the rdy/bsy pin is optional, and the pin does not need to be connected. xoutput vcc device power supply : the vcc pin is used to supply the source voltage to the device. program and erase operations are inhibited when v cc is less than or equal to v lko . operations at invalid v cc voltages may produce spurious results and should not be attempted. xxpower gnd ground : the ground reference for the power supply. gnd should be connected to the system ground. xxpower nc no connect : nc pins have no internal connections and can be driven or left floating. if the pins are driven, the voltage levels should comply with v ih and v il requirements. xx? res reserved : res pins are reserved for future device enhancements or functionality. these pins may be left floating or may be driven. if the pins are driven, the voltage levels should comply with v ih and v il requirements. these pins are used as the rdy/bsy and i/o[7:4] pins in the a/a mux interface. xx? table 1. signal descriptions (continued) symbol name and function interface type fwh/lpc a/a mux
6 at49lh002 3377b?flash?9/03 interface selection the at49lh002 can operate in two distinct interface modes: the fwh/lpc interface and the a/a mux interface. selection of the interface is determined by the state of the ic pin. when the ic pin is held low, the device will operate usi ng the fwh/lpc interface. alternatively, when the ic pin is held high, the device will operate using the a/a mux interface. fwh/lpc interface the fwh/lpc interface is designed as an in-system interface used in communicating with either the i/o controller hub (ich) in intel chipsets or typically the pci south bridge in non- intel chipsets. the fwh/lpc interface uses a 5-signal communication interface consisting of a 4-bit data bus, the fwh/lad[3:0] pins, and one control line, the fwh4/lframe pin. the operation and timing of the interface is based on the 33 mhz pci clock, and the buffers for the fwh/lpc interface are pci compliant. to ensure the effective delivery of security and manageability fea- tures, the fwh/lpc interface is the only way to get access to the full feature set of the device. commands, addresses, and data are transferred via the fwh/lpc interface using a series of fields. the field sequences and contents are strictly defined for fwh and lpc memory cycles. these field sequences are detailed in the fwh interface operation and lpc interface opera- tion sections. since the at49lh002 can be used as either a fwh flash or an lpc flash, the device is capable of automatically detecting which type of memory cycle is being performed. for a fwh/lpc cycle, the host will drive the fwh4/lframe pin low for one or more clock cycles to initiate the operation. after driving the fwh4/lframe pin low, the host will send a start value to indicate the type of fwh/lpc cycle that is to be performed. the value of the start field determines whether the device will operate using a fwh cycle or an lpc cycle. table 2 details the three valid start fields that the device will recognize. if a valid start value is not detected, then the device will enter standby mode when the fwh4/lframe pin is high and no internal operation is in progress. the fwh/lad[3:0] pins will also be placed in a high-impedance state. fwh4/lframe pin : fwh4/lframe is used by the master to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. this signal is to be used by peripherals to know when to monitor the bus for a cycle. the fwh4/lframe signal is used as a general notification that the fwh/lad[3:0] lines con- tain information relative to the start or stop of a cycle, and that peripherals must monitor the bus to determine whether the cycle is inte nded for them. the benefit to peripherals of fwh4/lframe is that it allows them to enter lower power states internally when a cycle is not intended for them. when peripherals sample fwh4/lframe is active, they are to immediately stop driving the fwh/lad[3:0] signal lines on the next clock and monitor the bus for new cycle information. table 2. fwh/lpc start fields start value cycle type 0000b lpc cycle ? the type (memory, i/o, dma) and direction of the cycle (read or write) is determined by the second field (cyctype + dir) of the lpc cycle. only memory cycles are supported by the device. 1101b fwh memory read cycle 1110b fwh memory write cycle
7 at49lh002 3377b?flash?9/03 fwh/lad[3:0] pins : the fwh/lad[3:0] signal lines communicate address, control, and data information over the lpc bus between a master and a peripheral. the information communi- cated are: start, stop (abort a cycle), transfer type (memory, i/o, dma), transfer direction (read/write), address, data, wait states, dma channel, and bus master grant. fwh memory cycles a valid fwh memory cycle begins with the host driving the fwh4/lframe signal low for one or more clock cycles. while the fwh4/lframe signal is low, a valid start value of either 1101b (fwh memory read) or 1110b (fwh memory write) must be driven on the fwh/lad[3:0] pins. following the start field, an idsel (device select) field must be sent to the device. the idsel field acts like a chip se lect in that it indicates which device should respond to the current operation. after the idsel field has been sent, the 7-clock maddr (memory address) field must be sent to the device to provide the 28-bit starting address loca- tion of where to begin reading or writing in the memory. following the maddr field, the msize (memory size) field must be sent to indicate the number of bytes to transfer. figure 1. fwh memory cycle initiation and addressing start field : this 1-clock field indicates the start of a cycle. it is valid on the last clock that fwh4/lframe is sampled low. the two start fields that are used for a fwh cycle are: 1101b to indicate a fwh memory read cycle and 1110b to indicate a fwh memory write cycle. if the start field that is sampled is not one of these values, then the cycle attempted is not a fwh memory cycle. it may be a valid lpc memory cycle that the device will attempt to decode. idsel (device select) field : this 1-clock field is used to indicate which fwh compo- nent in the system is being selected. the four bits transmitted over fwh/lad[3:0] during this clock are compared with values strapped on the id[3:0] pins. if there is a match, the device will continue to decode the cycle to determine which bytes are requested on a read or which bytes to update on a write. if there isn?t a match, the device may discard the rest of the cycle and go into a standby power state. maddr (memory address) field : this is a 7-clock field that is used to provide a 28-bit (a27 - a0) memory address. this allows for provisioning of up to 256 mb per fwh memory device, for a total of a 4 gb addressable space if 16 fwh memory devices (256 mb each) were used in a system. the at49lh002 only decodes the last six maddr nibbles (a23 - a0) and ignores address bits a27 - a23 and a21 - a18. address bit a22 is used to determine whether reads or writes to the device will be directed to the memory array (a22 = 1) or to the register space (a22 = 0). addresses are transferred to the device with the most significant nibble first. msize (memory size) field : the 1-clock msize is used to indicate how many bytes of data will be transferred during a read or write. the at49lh002 only supports single-byte transfers, so 0000b must be sent in this field to indicate a single-byte transfer. clk fwh4/lframe fwh/lad[3:0] start idsel maddr maddr maddr maddr maddr maddr maddr msize
8 at49lh002 3377b?flash?9/03 additional fields for fwh memory cycles additional fields are required to complete a fwh read or write cycle. the placement of these fields, in addition to the data field, depends on whether the cycle is a fwh read or write. the fwh read cycle and fwh write cycle sections detail the order of the various fields. tar (turn-around) field : this 2-clock field is driven by the master when it is turning control over to the fwh memory device, and it is driven by the fwh device when it is turning control back over to the master. on the first clock of the tar field, the master or fwh drives the fwh/lad[3:0] lines to 1111b. on the second clock, the master or fwh device puts the fwh/lad[3:0] lines into a high-impedance state. sync (synchronize) field : this field is used to add wait-states for an access. it can be several clocks in length. on target cycles, this field is driven by the fwh memory device. if the fwh device needs to assert wait-states, it does so by driving a ?wait? sync value of 0101b on the fwh/lad[3:0] pins until it is ready. when ready, the device will drive a ?ready? sync value of 0000b on the fwh/lad[3:0] lines. valid values for the sync field are shown in table 3. fwh read cycle fwh read cycles are used to read data from the memory array, the sector locking registers, the gpi register, the status register, and to read the product id information. upon initial device power-up or after exiting from a reset condition, the device will automatically default to the read array mode. valid fwh read cycles begin with a start field of 1101b being sent to the device. following the idsel, maddr, and msize fields, a 2-clock tar field must be sent to the device to indi- cate that the master is turning control of the lpc bus over to the fwh memory device. after the second clock of the tar phase, the fwh dev ice assumes control of the bus and begins driving sync fields to add wait-states. when the device is ready to output data, it will first send a ?ready? sync and then output one byte of data during the next two clock cycles. the data is sent one nibble at a time with the low nibble being output first followed by the high nib- ble. after the data has been output, the fwh device will send a 2-clock tar field to the master to indicate that it is turning control of the lpc bus back over to the master. figure 2 shows a fwh read cycle that requires three sync clocks to access data from the memory array. table 3. valid sync values sync value sync type 0000b rsync (ready sync) ? synchronization has been achieved with no error. 0101b wsync (wait sync) ? device is indicating wait-states (also referred to as short-sync).
9 at49lh002 3377b?flash?9/03 figure 2. fwh read cycle note: 1. field contents are valid on the rising edge of the present clock cycle. clk fwh4/lframe fwh/lad[3:0] 1101b idsel a15-a12 a27-a24 a23-a20 a19-a16 a11-a8 a7-a4 a3-a0 0000b high-z 0101b 0101b 0000b d3-d0 d7-d4 1111b high-z 1111b 12 6 3 4 5 7 8 9 10 12 13 14 15 16 17 18 19 11 start idsel maddr msize tar1 wsync wsync rsync data data tar0 tar1 tar0 table 4. fwh read cycle clock cycle field name field value (1) fwh/lad[3:0] fwh/lad[3:0] direction comments 1 start 1101b in fwh4/lframe must be active (low) for the device to respond. only the last start field (before fwh4/lframe transitioning high) should be recognized. the start field contents indicate a fwh memory read cycle. 2 idsel 0000b to 1111b in indicates which fwh memory device should respond. if the idsel field matches the strapping values on id[3:0], then that particular device will respond to subsequent commands. 3 - 9 maddr yyyy in these seven clock cycles make up the 28-bit memory address. yyyy is one nibble of the entire address. addresses are transferred with the most significant nibble first. 10 msize 0000b (indicates 1byte) in the msize field indicates how many bytes will be transferred. the device only supports single-byte operations, so msize must be 0000b. 11 tar0 1111b in then float in this clock cycle, the master has driven the bus to all 1s and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turn-around cycle?. 12 tar1 1111b (float) float then out the device takes control of the bus during this clock cycle. 13 - 14 wsync 0101b (wait) out the device outputs the value 0101b, a ?wait? sync, for two clock cycles. this value indicates to the master that data is not yet available from the device. this number of wait-syncs is a function of the device?s memory access time. 15 rsync 0000b (ready) out during this clock cycle, the device will generate a ?ready? sync indicating that the least significant nibble of the data byte will be available during the next clock cycle. 16 data yyyy out yyyy is the least significant nibble of the data byte. 17 data yyyy out yyyy is the most significant nibble of the data byte. 18 tar0 1111b out then float the fwh memory device drives the bus to 1111b to indicate a turn-around cycle. 19 tar1 1111b (float) float then in the fwh memory device floats its outputs, and the master regains control of the bus during this clock cycle.
10 at49lh002 3377b?flash?9/03 fwh write cycle fwh write cycles are used to send commands to the device and to program data into the memory array. valid fwh write cycles begin with a start field of 1110b being sent to the device. following the idsel, maddr, and msize fields, the master sends one byte of data to the fwh device during the next two clock cycles. the data is sent one nibble at a time with the low nibble being output first followed by the high nibble. afte r the data has been sent, the master will send a 2-clock tar field to the fwh device to indicate that it is turning control of the lpc bus back over to the fwh. after the second clock of the tar phase, the fwh device assumes control of the bus and drives a ?ready? sync field to verify that it has received the data. the fwh device will then send a 2-clock tar field to the mast er to indicate that it is turning control of the bus back over to the master. figure 3. fwh write cycle note: 1. field contents are valid on the rising edge of the present clock cycle. clk fwh4/lframe fwh/lad[3:0] 1110b idsel a15-a12 a27-a24 a23-a20 a19-a16 a11-a8 a7-a4 a3-a0 0000b high-z 0000b d3-d0 d7-d4 1111b high-z 1111b 12 6 3 4 5 7 8 9 10 12 13 14 15 16 17 11 start idsel maddr msize tar1 rsync data data tar0 tar1 tar0 table 5. fwh write cycle clock cycle field name field value (1) fwh/lad[3:0] fwh/lad[3:0] direction comments 1 start 1110b in fwh4/lframe must be active (low) for the device to respond. only the last start field (before fwh4/lframe transitioning high) should be recognized. the start field contents indicate a fwh memory write cycle. 2 idsel 0000b to 1111b in indicates which fwh memory device should respond. if the idsel field matches the strapping values on id[3:0], then that particular device will respond to subsequent commands. 3 - 9 maddr yyyy in these seven clock cycles make up the 28-bit memory address. yyyy is one nibble of the entire address. addresses are transferred with the most significant nibble first. 10 msize 0000b (indicates 1 byte) in the msize field indicates how many bytes will be transferred. the device only supports single-byte operations, so msize must be 0000b. 11 data yyyy in yyyy is the least significant nibble of the data byte. the data byte is either any valid flash command or the data to be programmed into the memory array. 12 data yyyy in yyyy is the most significant nibble of the data byte. 13 tar0 1111b in then float in this clock cycle, the master has driven the bus to all 1s and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turn-around cycle?. 14 tar1 1111b (float) float then out the device takes control of the bus during this clock cycle. 15 rsync 0000b (ready) out during this clock cycle, the device will generate a ?ready? sync indicating that the data byte has been received. 16 tar0 1111b out then float the fwh memory device drives the bus to 1111b to indicate a turn- around cycle. 17 tar1 1111b (float) float then in the fwh memory device floats its outputs, and the master regains control of the bus during this clock cycle.
11 at49lh002 3377b?flash?9/03 lpc memory cycles a valid lpc memory cycle begins with the host driving the fwh4/lframe signal low for one or more clock cycles. while the fwh4/lframe signal is low, a valid start value of 0000b must be driven on the fwh/lad[3:0] pins. following the start field, a cyctype + dir (cycle type and direction) field must be sent to the device to indicate the type of cycle (e.g., memory access, i/o access, etc.) and the direction (read or write) of the transfer. after the cyctype + dir field has been sent, the 8-clock maddr (memory address) field must be sent to the device to provide the 32-bit starting address location of where to begin reading or writing in the memory. figure 4. lpc memory cycle initiation and addressing start field : this 1-clock field indicates the start of a cycle. it is valid on the last clock that fwh4/lframe is sampled low. the start field that is used for an lpc cycle is 0000b. if the start field that is sampled is not 0000b, then the cycle attempted is not an lpc memory cycle. it may be a valid fwh memory cycle that the device will attempt to decode. cyctype + dir (cycle type and direction) field : this 1-clock field is used to indi- cate the type of cycle and the direction of the transfer to be performed. of the four bits placed on the fwh/lad[3:0] pins, bits[3:2] must be 01b to indicate that the transfer will be a memory cycle. values other than 01b, which may be used to specify an i/o cycle or a dma cycle for other components in the system, will cause the device to enter standby mode when the fwh4/lframe pin is brought high and no internal operation is in progress. the fwh/lad[3:0] pins will also be placed in a high-impedance state. bit[1] is used to determine the direction of the transfer. 0 is used to indicate a read, and 1 is used to indicate a write. bit[0] is ignored and reserved for future use. table 6 details the two valid cyctype + dir fields that the device will respond to. maddr (memory address) field : this is an 8-clock field that is used to provide a 32-bit (a31 - a0) memory address. the at49lh002 only decodes the last six maddr nibbles (a23 - a0) and ignores address bits a31 - a24 and a22 - a18. address bit a23 is used to determine whether reads or writes to the device will be directed to the memory array (a23 = 1) or to the register space (a23 = 0). addresses are transferred to the device with the most significant nibble first. table 6. valid cyctype + dir values fwh/lad[3:0] cycle type 010xb lpc memory read 011xb lpc memory write clk fwh4/lframe fwh/lad[3:0] start maddr maddr maddr maddr maddr maddr maddr maddr cyctype + dir
12 at49lh002 3377b?flash?9/03 additional fields for lpc memory cycles additional fields are required to complete an lpc read or write cycle. the placement of these fields, in addition to the data field, depends on whether the cycle is an lpc read or write. the lpc read cycle and lpc write cycle sections detail the order of the various fields. tar (turn-around) field : this 2-clock field is driven by the master when it is turning control over to the lpc memory device, and it is driven by the lpc device when it is turning control back over to the master. on the first clock of the tar field, the master or lpc device drives the fwh/lad[3:0] lines to 1111b. on the second clock, the master or lpc device puts the fwh/lad[3:0] lines into a high-impedance state. sync (synchronize) field : this field is used to add wait-states for an access. it can be several clocks in length. on target cycles, this field is driven by the lpc memory device. if the lpc device needs to assert wait-states, it does so by driving a ?wait? sync value of 0101b on the fwh/lad[3:0] pins until it is ready. when ready, the device will drive a ?ready? sync value of 0000b on the fwh/lad[3:0] lines. valid values for the sync field are shown in table 7. lpc read cycle lpc read cycles are used to read data from the memory array, the sector locking registers, the gpi register, the status register, and the product id information. upon initial device power-up or after exiting from a reset condition, the device will automatically default to the read array mode. valid lpc read cycles begin with a start field of 0000b and a cyctype + dir field of 010xb being sent to the device. following the maddr field, a 2-clock tar field must be sent to the device to indicate that the master is turning control of the lpc bus over to the lpc memory device. after the second clock of the tar phase, the lpc device assumes control of the bus and begins driving sync fields to add wait-states. when the device is ready to out- put data, it will first send a ?ready? sync and then output one byte of data during the next two clock cycles. the data is sent one nibble at a time with the low nibble being output first fol- lowed by the high nibble. after the data has been output, the lpc device will send a 2-clock tar field to the master to indicate that it is turning control of the lpc bus back over to the master. figure 5 shows a lpc read cycle that requires three sync clocks to access data from the memory array. table 7. valid sync values sync value sync type 0000b rsync (ready sync) ? synchronization has been achieved with no error. 0101b wsync (wait sync) ? device is indicating wait-states (also referred to as short-sync).
13 at49lh002 3377b?flash?9/03 figure 5. lpc read cycle note: 1. field contents are valid on the rising edge of the present clock cycle. clk fwh4/lframe fwh/lad[3:0] 0000b 010xb a15-a12 a27-a24 a31-a28 a23-a20 a19-a16 a11-a8 a7-a4 a3-a0 high-z 0101b 0101b 0000b d3-d0 d7-d4 1111b high-z 1111b 12 6 3 4 5 7 8 9 10 12 13 14 15 16 17 18 19 11 start maddr tar1 wsync wsync rsync data data tar0 tar1 tar0 cyctype + dir table 8. lpc read cycle clock cycle field name field value (1) fwh/lad[3:0] fwh/lad[3:0] direction comments 1 start 0000b in fwh4/lframe must be active (low) for the device to respond. only the last start field (before fwh4/lframe transitioning high) should be recognized. the start field contents indicate an lpc cycle. 2 cyctype + dir 010xb in indicates that the cycle type is an lpc memory cycle and the direction of the transfer is a read. 3 - 10 maddr yyyy in these eight clock cycles make up the 32-bit memory address. yyyy is one nibble of the entire address. addresses are transferred with the most significant nibble first. 11 tar0 1111b in then float in this clock cycle, the master has driven the bus to all 1s and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turn-around cycle?. 12 tar1 1111b (float) float then out the device takes control of the bus during this clock cycle. 13 - 14 wsync 0101b (wait) out the device outputs the value 0101b, a ?wait? sync, for two clock cycles. this value indicates to the master that data is not yet available from the device. this number of wait-syncs is a function of the device?s memory access time. 15 rsync 0000b (ready) out during this clock cycle, the device will generate a ?ready? sync indicating that the least significant nibble of the data byte will be available during the next clock cycle. 16 data yyyy out yyyy is the least significant nibble of the data byte. 17 data yyyy out yyyy is the most significant nibble of the data byte. 18 tar0 1111b out then float the lpc memory device drives the bus to 1111b to indicate a turn-around cycle. 19 tar1 1111b (float) float then in the lpc memory device floats its outputs, and the master regains control of the bus during this clock cycle.
14 at49lh002 3377b?flash?9/03 lpc write cycle lpc write cycles are used to send commands to the device and to program data into the memory array. valid lpc write cycles begin with a star t field of 0000b and a cyctype + dir field of 011xb being sent to the device. following the maddr field, the master sends one byte of data to the lpc device during the next two clock cycles. the data is sent one nibble at a time with the low nibble being output first followed by the high nibble. after the data has been sent, the master will send a 2-clock tar field to the lpc device to indicate that it is turning control of the bus back over to the lpc device. after the second clock of the tar phase, the lpc device assumes control of the bus and drives a ?ready? sync field to verify that it has received the data. the lpc device will then send a 2-clock tar field to the master to indicate that it is turn- ing control of the bus back over to the master. figure 6. lpc write cycle note: 1. field contents are valid on the rising edge of the present clock cycle. clk fwh4/lframe fwh/lad[3:0] 0000b 011xb a15-a12 a27-a24 a31-a28 a23-a20 a19-a16 a11-a8 a7-a4 a3-a0 high-z 0000b d3-d0 d7-d4 1111b high-z 1111b 12 6 3 4 5 7 8 9 10 12 13 14 15 16 17 11 start tar1 rsync data data tar0 tar1 tar0 maddr cyctype + dir table 9. lpc write cycle clock cycle field name field value (1) fwh/lad[3:0] fwh/lad[3:0] direction comments 1 start 0000b in fwh4/lframe must be active (low) for the device to respond. only the last start field (before fwh4/lframe transitioning high) should be recognized. the start field contents indicate an lpc cycle. 2 cyctype + dir 011xb in indicates that the cycle type is an lpc memory cycle and the direction of the transfer is a write. 3 - 10 maddr yyyy in these eight clock cycles make up the 32-bit memory address. yyyy is one nibble of the entire address. addresses are transferred with the most significant nibble first. 11 data yyyy in yyyy is the least significant nibble of the data byte. the data byte is either any valid flash command or the data to be programmed into the memory array. 12 data yyyy in yyyy is the most significant nibble of the data byte. 13 tar0 1111b in then float in this clock cycle, the master has driven the bus to all 1s and then floats the bus prior to the next clock cycle. this is the first part of the bus ?turn-around cycle?. 14 tar1 1111b (float) float then out the device takes control of the bus during this clock cycle. 15 rsync 0000b (ready) out during this clock cycle, the device will generate a ?ready? sync indicating that the data byte has been received. 16 tar0 1111b out then float the lpc memory device drives the bus to 1111b to indicate a turn-around cycle. 17 tar1 1111b (float) float then in the lpc memory device floats its outputs, and the master regains control of the bus during this clock cycle.
15 at49lh002 3377b?flash?9/03 response to invalid fwh/lpc fields during fwh/lpc operations, the device will not explicitly indicate that it has received invalid field sequences. the response to specific invalid fields or sequences is as follows: fwh cycles id mismatch : if the idsel field does not match id[3:0], then the device will ignore the fwh cycle. the device will then enter standby mode when the fwh4/lframe pin is brought high and no internal operation is in progress. the fwh/lad[3:0] pins will also be placed in a high-impedance state. address out of range : the fwh address sequences is seven fields long (28 bits), but only the last six address fields (a23 - a0) will be decoded. therefore, address bits a27 - a24 will be ignored. in addition, because of the device density, address bits a23 and a21 - a18 will be ignored. address bit a22 is used to determine whether reads or writes to the device will be directed to the memory array (a22 = 1) or to the register space (a22 = 0). invalid msize field : if the device receives an invalid size field during a read or write operation, the internal state machine will reset and no operation will be attempted. the device will generate no response of any kind in this situation. invalid size fields for a read or write cycle are anything but 0000b. in addition, when accessing register space, invalid field sizes are anything but 0000b. once valid start, idsel, and msize fields are received, the device will always respond to subsequent inputs as if they were valid. as long as the states of fwh/lad[3:0] and fwh4/lframe are known, the response of the device to signals received during the fwh cycle should be predictable. the device will make no attempt to check the validity of incoming flash operation commands. lpc cycles address out of range : the lpc address sequences is eight fields long (32 bits), but only the last six address fields (a23 - a0) will be decoded. therefore, address bits a31 - a24 will be ignored. in addition, because of the device density, address bits a22 - a18 will be ignored. address bit a23 is used to determine whether reads or writes to the device will be directed to the memory array (a23 = 1) or to the register space (a23 = 0). once valid start and cyctype + dir fields are received, the device will always respond to subsequent inputs as if they were valid. as long as the states of fwh/lad[3:0] and fwh4/lframe are known, the response of the device to signals received during the lpc cycle should be predictable. the device will make no attempt to check the validity of incoming flash operation commands. bus abort the bus abort operation can be used to immedi ately abort the current bus operation. a bus abort occurs when fwh4/lframe is driven low for one or more clock cycles after the start of a bus cycle. the memory will place the fwh/lad[3:0] pins in a high-impedance state, and the internal state machine will reset. during a write cycle, there is the possibility that an internal flash write or erase operation may be in progress (or has just been initiated). if the fwh4/lframe pin is asserted during this time frame, the internal operation will not abort. however, the internal state machine will not initiate a flash write or erase operation until it has received the last nibble from the host. this means that fwh4/lframe can be asserted as late as clock cycle 12 (see table 5 and tabl e 9) and no internal flash operation will be attempted. when the fwh4/lframe pin has been driven low to abort a cycle, the host may issue a start field of 1111b (stop/abort) to return the interface to the ready mode.
16 at49lh002 3377b?flash?9/03 device reset asserting rst or init initiates a device reset. in read mode, rst or init low deselects the memory, places the output drivers in a high-impedance state, and turns off all internal circuits. rst or init must be held low for the minimum specified t plph time (fwh/lpc and a/a mux operations). the device resets to read array mode upon return from reset, and all sector lock- ing registers are reset to their default (write-locked) state. since all sector locking registers are reset, all sectors in the memory array are set to the write-locked status regardless of their locked state prior to reset. a reset recovery time (t phfv using the fwh/lpc interface and t phav using the a/a mux inter- face) is required from rst or init switching back high until writes to the cui are recognized. a reset latency will occur if a reset procedure is performed during a programming or erase operation. during sector erase or program, driving rst or init low will abort the operation underway in addition to causing a reset latency. memory c ontents being altered are no longer valid since the data may be partially erased or programmed. it is important to assert rst or init during system reset. when the system comes out of reset, it will expect to read from the memory array of the device. if a system reset occurs with no fwh/lpc device reset (this will be hardware dependent), it is possible that proper cpu initial- ization will not occur (the fwh/lpc memory may be providing status information instead of memory array data). sector protection sectors in the memory array can be protected from program and erase operations using a hardware controlled method and/or a software (register-based) controlled method. hardware write protection two pins are available to provide hardware write protection capabilities. the top boot sector lock (tbl ) pin, when held low, prevents program and sector erase operations to the top sec- tor of the device (sector 6) where critical code can be stored. in addition, the tbl pin has the flexibility to provide erase protection to the top 64-kbyte region (sectors 6, 5, 4, and 3) of the device when the uniform sector erase command is used. this allows the tbl pin to protect a larger region for systems that require a 64-kbyte top boot sector rather than a 16-kbyte top boot sector. when the tbl pin is high, hardware write protection for program and erase operations to the top sector is disabled. provided that the write-lock bits in the sector locking registers are not set (detailed later), sector erase command s can then be issued to the device to erase either the top 16-kbyte sector (sector 6) or the entire top 64-kbyte region (sectors 6, 5, 4, and 3). program operations can also be performed to the top 16-kbyte sector. the write protect (wp ) pin, which operates independently from the tbl pin, serves the same basic function as the tbl pin for the remaining sectors except the top boot sector. when the wp pin is held low, program and standard sector erase command operations to sectors 5 through 0 will not be allowed. if using the uniform sector erase command, then erase opera- tions to sectors 2, 1, and 0 cannot be performed, and erase protection for sectors 6 through 3 will be controlled by the tbl pin.
17 at49lh002 3377b?flash?9/03 the tbl and wp pins must be set to the desired protection state prior to starting a program or erase operation because they are sampled at the beginning of the operation. changing the state of tbl or wp during a program or erase operation may cause unpredictable results. the new lock status will take place after the program or erase operation completes. the tbl and wp pins function independently from the sector locking registers. these pins, when active, will write protect the appropriate sector(s) against program and erase operations regardless of the values of the sector locking registers. for example, when tbl is active, writing to the top sector is prevented regardless of the state of the write-lock bit for the top sector?s locking register. in such a case, clearing the write-lock bit in the sector locking reg- ister will have no functional effect even though the register may indicate that the sector is no longer locked. however, the register may still be set to read-lock the sector if desired. for protecting the sectors of the memory array, the tbl and wp pins always take precedence over the sector locking registers. in addition, the states of the tbl and wp pins have no effect on the values or status of the sector locking registers. register-based sector locking the device has seven sector locking registers that are used in lieu of or in conjunction with the tbl and wp pins to control the lock protection for each sector in the memory array. the sector locking registers are accessed through their respective address locations (detailed in table 11) in the 4 gb system memory map. since the address bit used to distinguish between memory and register accesses differs when the device is used as a fwh or lpc flash (a22 for fwh and a23 for lpc), the register memory address will also differ. the sector locking registers are both readable and writable, and each register has three dedicated locking bits to control read lock, write lock, and lock down functions. therefore, a sector locking register can be read to determine what its current value is set to (e.g., set to lock down status). reading the sector locking registers, however, will not determine the status of the tbl and wp pins. when returning from a reset condition or after power-up, the sector locking registers will always default to a state of 01h. table 10. hardware write protection options sector size (bytes) address range hardware write protection for the following commands: sector erase (21h) byte program (40h or 10h) for the following command: uniform sector erase (20h) 6 16k 03c000h - 03ffffh tbl tbl 5 8k 03a000h - 03bfffh wp tbl 4 8k 038000h - 039fffh wp tbl 3 32k 030000h - 037fffh wp tbl 2 64k 020000h - 02ffffh wp wp 1 64k 010000h - 01ffffh wp wp 0 64k 000000h - 00ffffh wp wp
18 at49lh002 3377b?flash?9/03 read lock : the default read status of all sectors upon power-up is read-unlocked. when a sector?s read-lock bit is set (1 state), data cannot be read from that sector. an attempted read from a read-locked sector will result in data 00h being read (note that a read failure is not reflected in the status register). the read lock status can be unlocked by clearing (0 state) the read-lock bit, provided that the lock-down bit has not been set. the current read lock status of a particular sector can be determined by reading the corresponding read-lock bit. write lock : the default write status of all sectors upon power-up is write-locked (1 state). any program or erase operations attempted on a locked sector will return an error in the sta- tus register (indicating sector lock). the status of the locked sector can be changed to unlocked (0 state) by clearing the write-lock bi t, provided that the lock-down bit is not set. the current write lock status of a particular sector can be determined by reading the corre- sponding write-lock bit. the write-lock bit must be set to the desired protection state prior to starting a program or erase operation because it is sampled at the beginning of the operation. changing the state of the write-lock bit during a program or erase operation may cause unpredictable results. the new lock status will take place after the program or erase operation completes. the write lock functions independently of the hardware write protect pins, tbl and wp . when active, these pins take precedence over the re gister-based write lock function. changing the state of the tbl and wp pins will not affect the state of the write-lock bits. reading the sec- tor locking registers will not read the state of the tbl or wp pins. lock down : when in the fwh/lpc interface mode, the default lock down status of all sec- tors upon power-up is not-locked-down (0 state). the lock-down bit for any sector may be set (1 state), but only once, as future attempted changes to that sector locking register will be ignored. once a sector?s lock-down bit is set, the read-lock and write-lock bits for that sec- tor can no longer be modified, and the sector is locked down in its current state of read and write accessibility. the lock-down bit is only cleared upon a device reset with rst or init or after a power-up. the current lock down status of a particular sector can be determined by reading the corresponding lock-down bit. table 11. sector locking registers register name associated sector sector size (bytes) register memory address default value fwh mode lpc mode s6_lk 6 16k ffbfc002h ff7fc002h 01h s5_lk 5 8k ffbfa002h ff7fa002h 01h s4_lk 4 8k ffbf8002h ff7f8002h 01h s3_lk 3 32k ffbf0002h ff7f0002h 01h s2_lk 2 64k ffbe0002h ff7e0002h 01h s1_lk 1 64k ffbd0002h ff7d0002h 01h s0_lk 0 64k ffbc0002h ff7c0002h 01h
19 at49lh002 3377b?flash?9/03 general purpose input register a general-purpose input register is provided to read the stat us of the gpi[4:0] pins when using the fwh/lpc interface. since this is a pass-through register, there is no default value. it is recommended that the gpi[4:0] pins be in their desired state before fwh4/lframe is brought low for the beginning of the next bus cycle and remain in that state until the end of the cycle. table 12. function of sector locking bits bit name description 7:3 reserved reserved for future use. 2 read-lock 0 sector is not read-locked. normal read operations in the sector can occur. this is the default state. 1 sector is read-locked. read operations within the sector are prevented. data read will be 00h. 1 lock-down 0 sector is not locked down. the read-lock and write-lock bits may be changed. this is the default state. 1 sector is locked down. the read-lock and write-lock bits cannot be changed. once the sector is locked down, it will remain locked down until the device is reset (using the rst or init signals) or power-cycled. 0write-lock0 sector is not write-locked. normal program and erase operations to the sector can occur. 1 sector is write-locked. program and erase operations to the sector are prevented. this is the default state. table 13. valid sector locking register values data resulting sector state 07h sector is read and write locked down. 06h sector is read locked down. 05h sector is read and write locked but not locked down. 04h sector is read locked but not locked down. 03h sector is write locked down. 02h sector is locked open (full access locked down). 01h sector is write locked but not locked down. this is the default state. 00h sector is open for full access. table 14. gpi register memory address register name associated pins register memory address register type fwh mode lpc mode gpi_reg gpi[4:0] ffbc0100h ff7c0100h read only
20 at49lh002 3377b?flash?9/03 multiple device selection when used as a fwh device along with intel chipsets, multiple fwh devices may be used in a system to increase the overall memory density. by using the four id strapping pins, id[3:0], up to 16 fwh devices may be attached to the sa me bus. bios support, bus loading, or the attaching bridge may limit the actual number of devices that can be connected to the bus. the boot device must have id[3:0] equal to 0000b, and all subsequent devices should use sequential up-count strapping. the strapping values on id[3:0] must match the values in the idsel field when performing fwh memory cycles. the device will compare the values on the id[3:0] pins with the idsel field. if there is a mismatch, the device will ignore the remainder of the cycle. the device will then enter standby mode when the fwh4/lframe pin is high and no internal operation is in progress. the fwh/ lad[3:0] pins will also be placed in a high- impedance state. table 15. general-purpose input register bit name description 7:5 reserved reserved for future use. 4 gpi_reg4 0 gpi4 input pin is at v il . 1 gpi4 input pin is at v ih . 3 gpi_reg3 0 gpi3 input pin is at v il . 1 gpi3 input pin is at v ih . 2 gpi_reg2 0 gpi2 input pin is at v il . 1 gpi2 input pin is at v ih . 1 gpi_reg1 0 gpi1 input pin is at v il . 1 gpi1 input pin is at v ih . 0 gpi_reg0 0 gpi0 input pin is at v il . 1 gpi0 input pin is at v ih . table 16. fwh multiple device selection device id strapping pins idsel id3 id2 id1 id0 0 (boot device)0000 0000b 1 0001 0001b 2 0010 0010b 3 0011 0011b 4 0100 0100b 5 0101 0101b 6 0110 0110b 7 0111 0111b 8 1000 1000b 9 1001 1001b 10 1010 1010b 11 1011 1011b 12 1100 1100b 13 1101 1101b 14 1110 1110b 15 1111 1111b
21 at49lh002 3377b?flash?9/03 a/a mux interface the a/a mux interface is designed as a programming interface for oems to use during moth- erboard manufacturing or component pre-programming. the term a/a mux refers to the multiplexed row and column addresses that this interface utilizes. the a/a mux interface dra- matically reduces the amount of overhead needed to access the device, allowing the device to be tested and programmed quickly with automated test equipment (ate) and prom program- mers in the oem?s manufacturing flow. the number of signals required to use the interface does not change with device density; therefore, the interface can accommodate larger density devices while still allowing the device to fit into low lead-count packages. only basic read, erase, and program operations can be performed through the a/a mux inter- face; fwh/lpc features, such as the use of the sector locking registers and the general- purpose input register, are not available. the a/a mux interface mode is selected by driving the ic control pin high. the ic pin is inter- nally pulled down in the device, so a modest amount of leakage current should be expected to be drawn (see dc specifications) when the pin is driven high. four control pins dictate the flow of data into and out of the device: r/c , oe , we , and rst . the r/c pin is the a/a mux interface control pin used to latch row and column addresses. oe is the data output control pin for the i/o[7:0] lines and, when active, drives the selected mem- ory data onto the i/o bus (we and rst must be at vih). the we pin controls the flow of data into the device. addresses previously captured by the r/c pin transitions and data are latched into the device on the rising edge of we . the rst pin is used to reset the device. bus operation : all a/a mux bus cycles can be conformed to operate on most automated test equipment and prom programmers. notes: 1. x can be v il or v ih for control and address input pins. 2. v ih and v il refer to the dc characteristics associated with the flash memory output buffers: v il min = 0.5v, v il max = 0.8v, v ih min = 2.0v, v ih max = v cc + 0.5v. 3. refer to table 20 for product id addresses and data. output disable/enable : with oe at a logic-high level (v ih ), the device outputs are dis- abled. output pins i/o[7:0] are placed in the high-impedance state. with oe at a logic-low level (v il ), the device outputs are enabled. output pins i/o[7:0] are placed in an output-drive state. row/column addresses : r/c is the a/a mux interface control pin used to latch row (a10 - a0) and column address (a17-a11) values presented on the a[10:0] pins. r/c latches row addresses on the falling edge and column addresses on the rising edge. rdy/bsy : the open-drain ready/busy output pin pr ovides a hardware method of detecting the end of a program or erase operation. rdy/bsy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. table 17. a/a mux interface bus operations mode rst oe we address i/o[7:0] read (1)(2) v ih v il v ih xd out output disable (1)(2) v ih v ih v ih xhigh-z write (1)(2) v ih v ih v il xd in product id read (1)(2)(3) v ih v il v ih note 3 note 3
22 at49lh002 3377b?flash?9/03 device operation the fwh/lpc and a/a mux interfaces should be considered hardware interfaces that can be used to transfer commands and data to and from the device. the device commands detailed in table 18 can be issued using either interface. since the fwh/lpc interface communicates using a 4-bit data bus and the a/a mux interface utilizes an 8-bit data bus, the number of interface bus cycles needed to perform an operation will vary. for example, when using the fwh/lpc interface, 17 pci clock cycles are required for a fwh or lpc memory write cycle. therefore, for one ?write? device command cycle, 17 fwh/lpc bus cycles are needed. likewise, for one ?read? device command cycle using the fwh/lpc interface, 19 fwh/lpc bus cycles are required. notes: 1. the sector must not be hardware write protected or wr ite-locked when attempting sector erase or program operations. attempts to issue a sector erase or byte program command to a hardware write protected or write-locked sector will fail. 2. sub-sectors are sectors 6, 5, 4, and 3; the main sectors are sectors 2, 1, and 0. refer to the device memory map and table 10 for sector sizes and address ranges. the uniform sector erase command can be used to erase all sub-sectors at one time to allow uniform 64 kbytes sectors to be erased. a uniform sector erase command issued to any address in any one of the sub-sectors will cause all the sub-sectors to be erased pr ovided that all of the sub-sectors are not protected or write- locked. the standard sector erase command can be used to individually erase both the sub-sectors and the main sectors, allowing a single erase command to be used to erase any sector in the memory array. 3. either 40h or 10h is recognized by the device as the byte program command. 4. following the product id read command, read operations will access manufacturer and device id information. refer to table 20 for product id addresses and data. table 18. command definitions command command cycles 1st command cycle 2nd command cycle type address data type address data read array 1+ write any address ffh read any address data out sector erase (1)(2) 2write any address in the sector 21h write any address in the sector d0h uniform sector erase (1)(2) 2write any address in the sector 20h write any address in the sector d0h byte program (1)(3) 2write the address to be programmed 40h or 10h write the address to be programmed data in read status register 2 write any address 70h read any address status register data clear status register 1 write any address 50h product id read (4) 2write any address 90h read id address id data
23 at49lh002 3377b?flash?9/03 read array : upon initial device power-up and after exit from reset, the device defaults to the read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written to the device. once the internal write state machine (wsm) has started a sector erase or program operation, the device will not recognize the read array command until the operation is completed. sector erase : before a byte can be programmed into a sector, the sector must first be erased. the memory array is organized into multiple sectors that can be individually erased using two different sector erase commands, sector erase and uniform sector erase. the uni- form sector erase command can be used to erase the main sectors, and it can also be used to erase all of the sub-sectors to allow the memory array to be erased in uniform 64-kbyte regions. the sector erase command is used to erase the individual sub-sectors to provide a more efficient and finer erase granularity. in addition, the sector erase command can be used to erase the main sectors as well to allow a single erase command to be used to erase any sector in the memory array. both sector erase commands require two command cycles to ini- tiate the internally self-timed erase operation. after issuing a sector erase command, the device?s status register may be checked to deter- mine the status of the wsm and the erase operation. if the device detects a sector erase error, the status register should be cleared before the system software attempts any corrective actions. after a sector erase, the cui remains in the read status register mode until a new command is issued. successful sector erase requires that the corresponding sector?s write-lock bit be cleared and the corresponding hardware write protect pin (tbl or wp ) be inactive. if using the uniform sector erase command to erase all of the sub-sectors, then all of the sub-sectors must have their write-lock bits cleared and the tbl pin must be inactive. if a sector erase is attempted when the sector is locked, the sector erase will fail, and the reason for the failure will be indi- cated in the status register. the erased state of the memory bits is a logical ?1? (erased state of a byte is ffh). byte program : the device is programmed on a byte-by-byte basis. the byte program command requires two command cycles with the programming address and data being input on the second command cycle. the device will automatically generate the required internal programming pulses, and all programming operations are completely self-timed. please note that the byte location being programmed must have already been erased to ffh. a ?0? cannot be programmed back to a ?1?; only an erase operation can convert ?0?s to ?1?s. after the byte program command is written, the device?s status register may be checked to determine the wsm status and the result of the program operation. if a program error is detected, the status register should be cleared before any corrective action is taken by the system software. after a byte program operation, the cui remains in the read status register mode until a new command is issued. a successful program operation also requires that the corresponding sector?s write-lock bit be cleared, and the corresponding hardware write protect pin (tbl or wp ) be inactive. if a pro- gram operation is attempted when the sector is locked, the operation will fail, and the reason for the failure will be indicated in the status register. read status register : the status register (sr) may be read to determine when a sec- tor erase or program operation completes and whether the operation completed successfully. the status register may be read at any time by writing the read status register command. after writing the read status register command, all subsequent read operations will return data from the status register until another valid command is written to the device. clear status register : error flags (sr[5,4,1]) in the status register can only be set to ?1?s by the wsm and can only be reset by th e clear status register command. therefore, if an error is detected, the status register must be cleared before beginning another operation to avoid ambiguity.
24 at49lh002 3377b?flash?9/03 note: 1. sr[1] does not provide a continuous indication of the write-lock bit, tbl pin, or wp values. the wsm interrogates the write-lock bit, tbl pin, or wp pin only after a sector erase or program operation. depending on the attempted operation, it informs the system whether or not the selected sector is locked. product id read : the product id read mode is used to identify the product type and the manufacturer as atmel. fol- lowing the product id read command, read cycles from the addresses shown in table 20 retrieve the manufacturer and device id code. to exit the product id read mode, any valid command can be written to the device. table 19. status register (sr) sr bit name description 7 write state machine status (wsm) 0 device is busy. a program or erase cycle is in progress. sr[6-1] values are invalid when sr[7] is 0. 1 device is ready. the device is ready for any operation. 6 reserved reserved for future use. 5erase status 0 erase successful. the sector erase operation completed successfully. 1 erase failed. the sector erase operation failed. if sr[5,4] are 1, then there was a command sequence error. 4 program status 0 program successful. the byte program operation competed successfully. 1 program failed. the program operation failed. if sr[5,4] are 1, then there was a command sequence error. 3:2 reserved reserved for future use. 1 device protect status (1) 0 sector is unlocked. the sector being erased or programmed is unlocked (not protected). 1 sector is hardware write protected or write-locked. the sector being erased or programmed is either hardware write protected by the tbl or wp pin, or it is write-locked. 0 reserved reserved for future use. table 20. product id address and data code address data manufacturer id 000000h 1fh device id 000001h e9h
25 at49lh002 3377b?flash?9/03 notes: 1. all specified voltages are with respect to gnd. during transitions, this level may undershoot to -2.0v for periods of < 20 ns. during transitions, this level may overshoot to v cc + 2.0v for periods <20 ns. 2. do not violate processor or chipset limitations on the init pin. note: 1. the device is designed to operate at temperatures beyond the normal commercial temperature range of 0 c to +70 c. notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all packages. 2. v ih = 0.9 v cc , v il = 0.1 v cc per the pci output v oh and v ol spec. absolute maximum ratings* voltage on any pin ...................-0.5v to +vcc + 0.5v (1)(2) *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating conditions temperature and v cc symbol parameter test condition min max unit t c operating temperature (1) case temperature 0 +85 c v cc v cc supply voltage 3.0 3.6 v power supply specifications ? all interfaces symbol parameter conditions min max units v lko v cc lockout voltage 1.5 v i ccsl1 v cc standby current (fwh/lpc interface) voltage range of all inputs is v ih to v il , fwh4/ lframe = v ih , (2) v cc = 3.6v, f clk = 33 mhz no internal operations in progress 35 a i ccsl2 v cc standby current (fwh/lpc interface) fwh4/ lframe = v il (2) v cc = 3.6v, f clk = 33 mhz no internal operations in progress 2ma i cca v cc active read current (fwh/lpc interface) v cc = v cc max, fwh4/ lframe = v il (2) f clk = 33 mhz i out = 0 ma 15 ma i pp program or erase current v cc = v cc max 55 ma
26 at49lh002 3377b?flash?9/03 notes: 1. inputs are not ?5-volt safe.? 2. do not violate processor or chipset specifications regarding the init pin voltage. 3. input leakage currents include high-z output leakage for all bi-directional buffers with high-z outputs. 4. i il may be higher on the ic and id pins (up to 200 a) if pulled against internal pull-downs. refer to the pin descriptions 5. refer to pci spec. notes: 1. pci specification output load is used. 2. i oh = (98.0/v cc ) * (v out - v cc ) * (v out + 0.4 v cc ). 3. i ol = (256/v cc ) * v out (v cc - v out ). fwh/lpc interface dc input/output specifications symbol parameter conditions min max units v ih (1) input high voltage 0.5 v cc v cc + 0.5 v v ih (init ) (1)(2) init input high voltage 1.35 v cc + 0.5 v v il input low voltage -0.5 0.3 v cc v v il (init ) (2) init input low voltage 0.85 v i il (3)(4) input leakage current 0 < v in < v cc 10 a v oh output high voltage i out = -500 a 0.9 v cc v v ol output low voltage i out = 1.5 ma 0.1 v cc v c in input pin capacitance 13 pf c clk clk pin capacitance 3 12 pf l pin (5) recommended pin inductance 20 nh fwh/lpc interface ac input/output specifications symbol parameter condition min max units i oh (ac) switching current high 0 < v out 0.3 v cc -12 v cc ma 0.3 v cc < v out < 0.9 v cc -17.1 (v cc - v out )ma 0.7 v cc < v out < v cc note 2 (test point) v out = 0.7 v cc -32 v cc ma i ol (ac) switching current low v cc > v out 0.6 v cc 16 v cc ma 0.6 v cc > v out > 0.1 v cc -17.1 (v cc - v out )ma 0.18 v cc > v out > 0 note 3 (test point) v out = 0.18 v cc 38 v cc ma i cl low clamp current -3 < v in -1 -25 + (v in + 1)/0.015 ma i ch high clamp current v cc + 4 > v in v cc + 1 25 + (v in - v cc - 1)/0.015 ma slewr output rise slew rate 0.2 v cc - 0.6 v cc load (1) 14v/ns slewf output fall slew rate 0.6 v cc - 0.2 v cc load (1) 14v/ns
27 at49lh002 3377b?flash?9/03 fwh/lpc interface ac timing specifications notes: 1. pci components must work with any clock frequency between nominal dc and 33 mhz. frequencies less than 16 mhz may be guaranteed by design rather than testing. 2. applies only to rising edge of signal. clock waveform clock specification symbol parameter condition min max units t cyc clk cycle time (1) 30 ns t high clk high time 11 ns t low clk low time 11 ns ? clk slew rate peak-to-peak 1 4 v/ns ?rst or init slew rate (2) 50 mv/ns t cyc t high t low 0.6 v cc 0.5 v cc 0.4 v cc 0.3 v cc 0.4 v cc, p-to-p (minimum) 0.2 v cc
28 at49lh002 3377b?flash?9/03 notes: 1. minimum and maximum times have different loads. see pci spec. 2. for purposes of active/float timing measurements, the high-z or ?off? state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 3. this parameter applies to any input type (excluding clk). output timing parameters input timing parameters signal timing parameters symbol pci symbol parameter min max units t chqx t val clk to data out (1) 211ns t chqx t on clk to active (float to active delay) (2) 2ns t chqz t off clk to inactive (active to float delay) (2) 28 ns t avch t dvch t su input set-up time (3) 7 ns t chax t chdx t h input hold time (3) 0 ns t vspl t rst reset active time after power stable 1 ms t cspl t rst-clk reset active time after clk stable 100 s t plqz t rst-off reset active to output float delay (2) 48 ns t off t on t val v th v tl v test clk fwh/lad[3:0] (valid output data) fwh/lda[3:0] (float output data) t h v th v tl v max v test clk fwh/lad[3:0] (valid input data) t su inputs valid
29 at49lh002 3377b?flash?9/03 note: 1. the input test environment is done with 0.1 v cc of overdrive over v ih and v il . timing parameters must be met with no more overdrive than this. v max specifies the maximum peak-to-peak waveform allowed for measuring the input timing. production testing may use different voltage values, but must correlate results back to these parameters. note: 1. a reset latency of 20 s will occur if a reset procedure is performed during a programming or erase operation. ac waveform for reset operation notes: 1. typical values measured at t a = +25 c and nominal voltages. 2. excludes system-level overhead. interface measurement condition parameters symbol value units v th (1) 0.6 v cc v v tl (1) 0.2 v cc v v test 0.4 v cc v v max (1) 0.4 v cc v input signal edge rate 1 v/ns reset operations symbol parameter min max unit t plph (1) rst or init pulse low time (if rst or init is tied to v cc , this specification is not applicable) 100 ns t phfv rst or init high to fwh4/frame low 1 s programming and erase times parameter typ (1) max unit byte program time (2) 30 50 s sector erase time (2) 150 500 ms v ih v il rst t plph t phfv v ih v il fwh4/lframe
30 at49lh002 3377b?flash?9/03 electrical characteristics for a/a mux interface: certain specifications differ from the previous sections when programming using the a/a mux interface. the following subsections provide this data. any information that is not shown here is not specific to the a/a mux interface and uses the fwh/lpc interface specifications. notes: 1. inputs are not ?5-volt safe.? 2. input leakage currents include high-z output leakage for all bi-directional buffers with high-z outputs. 3. i il may be higher on the ic and id pins (up to 200 a) if pulled against internal pull-downs. refer to the pin descriptions. 4. refer to pci spec. notes: 1. if rst is asserted when the wsm is not busy (rdy/bsy = 1), the reset will complete within 100 ns. 2. a reset recovery time, t phav , is required from the latter of rdy/bsy or rst going high until addresses are valid. ac waveforms for reset operations a/a mux interface dc input /output specifications symbol parameter conditions min max unit v ih (1) input high voltage 0.5 v cc v cc + 0.5 v v il input low voltage -0.5 0.8 v i il (2)(3) input leakage current v cc = v cc max, v out = v cc or gnd + 10 a v oh output high voltage v cc = v cc min, i oh = -2.5 ma v cc = v cc min, i oh = -100 a 0.85 v cc min v cc = 0.4 v v v ol output low voltage v cc = v cc min, i ol = 2 ma 0.4 v c in input pin capacitance 13 pf c clk clk pin capacitance 3 12 pf l pin (4) recommended pin inductance 20 nh reset operations symbol parameter min max unit t plph rst pulse low time (if rst is tied to v cc , this specification is not applicable.) 100 ns t plrh rst low to reset during sector erase or program (1)(2) 20 s t phav rst high to row address setup (2) 1s v ih v il v ih v il t plph t phav t plrh t phav rdy/bsy rst v ih v il address
31 at49lh002 3377b?flash?9/03 note: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe may be delayed up to t chqv - t glqv after the rising edge of r/c without impact on t chqv . 3. t c = 0 c to +85 c , v cc = 3.0v to 3.6v. a/a mux read timing diagram a/a mux interface read-only operations (1)(3) symbol parameter min max units t avav read cycle time 250 ns t avcl row address setup to r/c low 50 ns t clax row address hold from r/c low 50 ns t avch column address setup to r/c high 50 ns t chax column address hold from r/c high 50 ns t chqv r/c high to output delay (2) 150 ns t glqv oe low to output delay (2) 50 ns t phav rst high to row address setup 1 s t glqx oe low to output in low-z 0 ns t ghqz oe high to output in high-z 50 ns t qxgh output hold from oe high 0 ns v ih v il r/c v ih v il oe v ih v il we v ih v il rst v oh v ol i/o v ih v il addresses t glqx t chax t avch t clax t avcl t qxgh t ghqz t glqv t chqv t phav t avav row address stable next address stable data valid high-z high-z column address stable
32 at49lh002 3377b?flash?9/03 note: 1. t c = 0 c to +85 c, v cc = 3.0v to 3.6v. a/a mux write timing diagram a/a mux interface write operations (1) symbol parameter min max units t phwl rst high recovery to we low 1 s t wlwh write pulse width low 100 ns t dvwh data setup to we high 50 ns t whdx data hold from we high 5 ns t avcl row address setup to r/c low 50 ns t clax row address hold from r/c low 50 ns t avch column address setup to r/c high 50 ns t chax column address hold from r/c high 50 ns t whwl write pulse width high 100 ns t chwh r/c high setup to we high 50 ns t whgl write recovery before read 150 ns t whsv write recovery before a valid srd (status register data) read 150 ns t whrl we high to rdy/bsy going low 0 ns v ih v il r/c v ih v il we v oh v ol i/o v ih v il rdy/bsy v ih v il rst v ih v il oe v ih v il addresses t whrl t whdx t chwh t chax t clax t avch t avcl t whwl t wlwh t dvwh t whsv t whgl t phwl r1 c1 r2 c2 valid srd d in d in ab c d e f ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? notes a=v cc power-up and standby b = write sector erase or program setup c = write sector erase confirm or valid address and data d = automated erase or program delay e = read status register data f = ready to write another command
33 at49lh002 3377b?flash?9/03 ordering information i cc (ma) ordering code package operation range active standby 15 0.03 at49lh002-33jc AT49LH002-33TC 32j 40t extended commercial (0 to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier package (plcc) 40t 40-lead, thin small outline package (tsop)
34 at49lh002 3377b?flash?9/03 packaging information 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
35 at49lh002 3377b?flash?9/03 40t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40t , 40-lead (10 x 20 mm package) plastic thin small outline package, type i (tsop) b 40t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation cd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 9.90 10.00 10.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
printed on recycled paper. 3377b?flash?9/03 xm disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products , expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof are the registered trademarks of atmel corporation or its subsidiaries. intel ? is a registered trademark of intel corporation. other terms and product names may be the trademarks of others.

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